Videos > Ansys HFSS/Circuit : PCIe template
May 12, 2023

PCI Express Template Tutorial

Introduction

Hi, my name is Hatem Akel. I'm an application engineer with Ozen Engineering, Inc. This short tutorial will show you how to use the PCI Express template.

Model Overview

As you can see, we have models for every standard. If you open any one of them, you will see these circuits. In these models, we used filters to present channels, but as a user, you can remove them and replace them with S-parameters.

Uploading S-Parameters

  1. Click on the import icon.
  2. Select your S-parameter files.
  3. You can upload a minimum of one channel or multiple channels to see the effect of crosstalk on signal integrity.
  4. If you upload one channel, attach it to the second circuit.

Circuit Setup and Specifications

Within these circuits, the setup and graphs are designed according to the specifications:

  • Data rate, rising time, and voltage are entered as per the specifications.
  • Equalization setup (FFE) with the number of taps as specified.
  • On the RX side (iPRO), DFE and CTLE are configured. For PCIe 5, there is a gain ADC that affects the second zero of the CTLE.

To know the allowed values for the gain, check the optometric setup.

Effect of Equalization

We have three circuits at the bottom used to study the effect of equalization:

  • First circuit: CTLE removed.
  • Second circuit: CTLE and DFE removed.
  • Third circuit: All equalizations removed from TX and RX.

Graphical Analysis

Running these models will generate numerous graphs with specifications:

  • Width Specification:
    • Limits are shown as per specifications.
    • Specification requires the width at 1e-12 contour to be greater than 0.3.
    • Markers are used to measure and display the eye width.
  • Height Specification:
    • Delta between two points must be greater than 15mV peak to peak.
    • Example shows around 311mV peak to peak due to ideal structure.
  • Eye Diagrams:
    • Eye diagram parameters are calculated and displayed.
    • Diagrams are available for cases with no CTLE, no DFE, and no equalizations.
  • Stressed Eye:
    • Nominal results with added jitter at the receiver input.
    • Generate a bathtub plot by adding random, deterministic, sinusoidal, and DSD1 jitter.
    • Analyze the effect of jitter on eye width.

Importing HFSS Models

Instead of using S-parameter files, you can create a dynamic link with HFSS models:

  • Copy your HFSS model inside the template.
  • Create a dynamic link with the HFSS model.

Frequency Specifications

For PCIe 5, the specification is from DC to 16 GHz, and for PCIe 3, it is from 0 to 4 GHz. Beyond these frequencies, there is no specification.

Additional Calculations

  • Differential and Common Mode Return Loss:
    • Graphs are available for both differential and common mode return loss.
  • Skew Calculations:
    • Requires a model of at least two channels.
    • Calculates skew between P and N using a complex formula.
  • TDR Circuit:
    • Simple circuit with TDR probe to study impedance within the channel.
  • Crosstalk Debugging:
    • Debugs crosstalk in simulations or measurements.
    • Analyzes two channels to locate crosstalk and its amplitude.

Conclusion

Thank you for listening.

[This was auto-generated. There may be mispellings.]

Hi, my name is Hatem Akel. I'm an application engineer with OZEN Engineering. This short tutorial will show you how to use the PCI Express template. As you can see, we have models for every standard. If you open any one of them, you will see these circuits.

In these models, what we did is we used filters to present channels, but for you as a user, you can remove them and replace them with S-parameters. And the way you upload S-parameter files is by clicking on this icon and importing, and from there, you can select your S-parameter files.

You can upload one channel, a minimum of one channel, or you can upload two or three channels file. If you upload more than one channel, you can see the effect of crosstalk on the signal integrity of your signal. If you upload one channel, attach it to the second circuit here.

Within these circuits, the setup and the graphs are designed according to the specifications. If I double click on the source of our signal, you will find that we entered the data. The data rate, the rising time, and the voltage as per the specifications.

Also, if you look at the equalization setup, FFE, the number of tabs is as in the specifications. And the same thing happens on the RX side, which is the iPro. The DFE and the CTLE, and you notice here for the PCIe 5, there is the gain ADC.

And based on the gain, if you change the gain, this is a variable. If you change the gain, that will change the second zero of the CTLE. To know what are the allowed values as per the specifications for the gain, just check the optometric setup. We also have these three circuits at the bottom.

These circuits are used to study the effect of equalization. In this model here, for example, we remove the CTLE. Here, we remove the CTLE and the DFE. And in the last circuit, we removed all the equalizations from the TX and from the RX. Now let's return to the interface.

This is an example of the other approach, which allows you to study the effect of equalization on your circuit. If you run these models, you will get so many graphs, and there we will have more specifications.

So, if I go to, for example, the width spec, you will get something like this, where the limits shown here are as per the specifications.

This specification wants the width at the 1e-12 contour to be greater than 0. 3. So, the way we do it is by simply creating this kind of markers, then we copy the delta to a variable and we display this variable as a clean line.

Then we put another marker, and that's how we know what's our specification. So, let's go to the next one. The Y value represents the eye width and it has to be greater than 0. 3. You also can see the high spec. We have here a contour plot. The only problem is it's a contour plot.

Contour plots are like paint. The markers cannot snap to the curve, so you have to move them to snap to them and that will give you a nice, clean line. So, let's go to the next one. The height versus the specifications.

As you can see, the spec here is that the delta between these two has to be greater than 15mV peak to peak. And you see we have here around 311mV peak to peak, simply because we have an ideal structure in our circuit. You can see the results of the case where there is no CTLE.

In this case, we have the ideal structure. So, it's the same diagram. You can take a look at it. Every time you display an eye diagram to the left, you see all the different parameters of the eye diagram calculated for you.

We can also see the eye diagram of the no CTLE and no DFE case and the last one for no equalizations. And finally, at the last graph, we have here what we call the stressed eye. So, the stressed eye is simply the same nominal results but with jitter at the input of the receiver.

So, the way we create the bathtub, if you want to have more cases, you go to a rectangular plot and from here, you activate this option, which is distributing and adding jitter.

As you can see, here, you can override the numbers and add random, deterministic, sinusoidal, and DSD 1. You can also add noise if you want. Then generate the bathtub and from there, you can tell the effect of the jitter on the width of your eye.

Going back to the circuit, I mentioned that you can import S-parameter files. There is another way where you have HFSS models for example. What you can do is copy your HFSS model inside this template. Then you create a dynamic link.

So, instead of getting an S-parameter file, you can now create a dynamic link with an HFSS model. And there are some other ways to do this. For example, you can create a dynamic link with an HFSS model. And there are some other ways to do this.

For example, you can create a dynamic link with an HFSS model. And there are some other ways to do this. For example, you can create a dynamic link with an HFSS model. And there are some other ways to do this. For example, you can create a dynamic link with an HFSS model.

And there are some other ways to do this. For example, you can create a dynamic link with an HFSS model. And there are some other ways to do this. For example, you can create a dynamic link with an HFSS model. And there are some other ways to do this.

For example, you can create a dynamic link with an HFSS model. And there are some other ways to do this. For example, if you are studying PCIe 5, then the spec is from DC to 16 gig. Anything beyond that is not part of that spec.

The same thing if you are doing for example PCIe 3, it is from 0 to 4 gig, and after 4 gig, there is no spec. So, that's how you read it. We have a graph for the differential return loss and another one for the common mode return loss.

Now, we have also other calculations like the skew between differential lines. Of course, if you go to that circuit, you need to have at least a model of two channels. There are also the skew between P and N for people who are interested in knowing how much is the skew between P and N.

This circuit will do it and it will calculate the skew not based on physical information or delay. No, it takes the differential and the common results. It uses a complicated formula like the one you see here in order to be able to calculate the skew between P and N in the proper way.

We also have the TDR, the TDR circuit, which is again a very simple circuit as you can see. We have the TDR probe. The TDR is very simple and very easy to use. As you can see, we have the TDR probe. You can use it to study the impedance within your channel.

And the last circuit I would like to talk about is the crosstalk debugging. This is a very important addition to the project. It allows you to debug crosstalk, whether you are looking at the crosstalk in your simulation or you are looking at the crosstalk in your measurement.

All you need to do is to bring the measurements or the simulations of two channels, plug them here, and immediately the system will give you the analysis and tell you exactly the location of the crosstalk.

So, you see here the first line will be the green one, representing the victim TDR, which will show you the differential the different transitions within your victim.

But the other curve will show the crosstalk where the crosstalk is happening and how much is the amplitude of the crosstalk at each one of these bad locations. And by looking at both these two curves, you will be able to tell where the crosstalk is happening.

Then you can focus on the ones with the worst amplitude and improve the isolation in these locations to suppress crosstalk. Thank you for listening.