Smart Voltage-Controlled Current Source in SaberRD – Concept & Design

Smart Voltage-Controlled Current Source in SaberRD – Concept & Design Hi everyone, this is Majid Heidari. Today, I will show you how we can design and simulate a voltage-controlled current source using SaberRD.

This tool allows us to combine analog, digital, and system-level components into one simulation. For instance, in this picture, you see an FPGA, sensor, ASIC, and load; you see a mixed-signal, analog, and digital setup. I will show you how we can start a simulation and mix signals.

First, let's look at SaberRD's capabilities. The first thing is multi-domain modeling. We can model using MAST or VHDL-AMS, or we can reuse SPICE models and even bring in C or MATLAB models. This lets us work at different levels, from simple behavioral blocks to fully physics-based details.

Also, Saber connects with other tools like MATLAB, Simulink, and it supports FMI and FMU. This means we can exchange models with other simulations and link our work into a large system flow. Another topic is the analysis of Saber. Saber helps us to check robustness and safety.

We can run parametric sweeps, multicolor analysis, sensitivity analysis, and even support fault injection and standards like ISO 26262 and ISO 26262 for functional safety. So, it's a digital and analog synergy. As you see here, I showed a voltage-controlled current source design.

We have an FPGA or microcontroller to generate a bit stream for us. We have a sensor, we have an op-amp, we have comparator logic, and we have some other logic. For instance, we have D2R.

D2R converts digital pin transitions into another control signal, and then we have control to current, which actually converts the unitless control signal into an electrical current. So, let's see how we can model this circuit.

I will show a demo of Saber in the next video, but in this video, I will mostly focus on the concept. Here, as you see, if you are using a sensor, we have a sinusoidal signal, and for the FPGA and microcontroller, we have a pulse. So, these are our inputs.

Now, I will show you how we can model a comparator logic with Saber. So, how does comparator logic work? If Vin is greater than VH, the output goes high. You can see the description of our comparator logic here. I want to model this comparator logic with an HDL language.

So, let's see; this is VHDL-AMS. As you see, when we are modeling with an HDL language, it's a little bit different from conventional languages. We can do parallel analysis with an HDL language. As you see here, we model the op-amp and the comparator.

This block waits for any changes on enable, VIN above VH, or VIN above VL. If something happens, then we have some if-else statements. You can see how we can model this comparator with VHDL-AMS. Now, this is the output of the comparator logic.

Exactly, you can see the hysteresis behavior; you can see VH and VL, and how the comparator generates this pulse for us. In the GUI of the comparator, you can access and change and modify this parameter, like offset, positive offset, and offset in the negative port, so you can put the hysteresis.

This is the input of the AND gate, generated by the microcontroller or FPGA, and this is the output of the AND gate. You can see, because of this delay that we put for the AND gate, which is around 1 millisecond, we can see a 1-millisecond delay in the output.

Now, if you look at the D2 wire, the D2 wire converts the signal to an analog signal. This is a black pulse signal, and you can see the load here.

What you can see is that the load is followed by our sensor signal, and then if the voltage goes beyond 3.2, the feedback inverter goes to low, and then the output of the AND gate goes to 0. The load resistor runs a transient analysis, measures the RMS value, and plots the behavior of the load versus time.

Let's look at how we can define an experiment. As you see here, we changed the resistor from 3k to 10k with 5 points and with multi-core simulation to speed up the simulation. And then we have a transient analysis in 100 ms. So, we measured all signals here.

Then, we measured the RMS load and see what the result looks like. Here are the results. The top shows the waveform versus time for the load, and here it shows the RMS versus different resistor values. In this step, we can extend the experiments by adding a pass-fail condition.

For instance, I put the test: if RMS load is greater than 1.6, it's passed; below 1.6, it's failed. This is great; it makes it easy to verify design requirements during simulation. Instead of manually inspecting the waveforms, Saber can directly confirm whether the performance criteria are met.

Great tool! I will show you how we can model and simulate this current source in SaberRD in the next video. See you in the next video! Please contact us at https://ozeninc.com/contact for more information.