- July 19, 2019
9:00 am - 5:00 pm
- July 6, 2018
9:00 am - 5:00 pm
The ANSYS HFSS 3D Layout course for high-speed printed circuit board design focuses on layered structures using the 3D Layout design type in HFSS and AEDT (ANSYS Electronic Desktop). Designed for brand new users, this course covers layer stack-up, layout viewing, choices of solvers, ports, pad-stacks, and hierarchy. Workshops include small differential via structures, larger full-PCB structures and simulations, and sub-design cutouts from larger printed circuit boards. Several workshops follow a realistic workflow from start to finish and several workshops include transient circuit simulation of EM (electromagnetic) models.
As a complement to the traditional arbitrary 3D CAD-based modeling interface, the HFSS 3D Layout interface is a significant productivity enhancement for IC Package and PCB designers. HFSS 3D Layout allows engineers to easily create fully parametric models and perform design studies of printed circuit boards (PCB), electronic Packages and custom integrated circuits. During this training course both Package and PCB examples will be used to highlight the functionality and automation provided by HFSS and how to improve performance and productivity. In addition, the built-in parametric interface enables design engineers to explore design alternatives and evaluate design trade-offs prior to fabrication. Complementing the engineering efficiency, a set of advanced technologies will be presented that enable faster HFSS simulations through the application of High-performance computing (HPC).
The course also includes relevant “hands-on” workshops and exercises.
Target Audience: Engineers and Designers
Teaching Method: Lectures and computer practical sessions to validate acquired knowledge. A training certificate is provided to all attendees who complete the course.
9:00AM – Class Begins
12- 1:00PM – Lunch Served
5:00PM – Class Ends