Ansys SIwave-DC

Integrated & Automated DC I²R Reporting

Ansys SIwave-DC targets DC analysis of low-voltage, high-current PCB and IC packages, enabling assessment of critical end-to-end voltage margins to ensure reliable power delivery. It allows users to perform pre- and post-layout what-if analyses for DC voltage drop, DC currents and DC power loss. This process ensures that power distribution networks (PDNs) can source the proper power to integrated circuits — checking that the PDN has the proper bump, ball and pin sizes as well as proper copper weighting to minimize losses — and identify areas of excess current, which can result in thermal hot spots, to reduce risk of field failure.

The SIwave-DC solver was developed specifically for planar ECAD geometries. The entire structure is discretized into a number of finite elements, and a variational technique (finite element method, or FEM) computes voltage and current distribution across an entire power delivery network. In general, the overall accuracy of an FEM-based solver depends on two factors: the accuracy with which a mesh can match design geometry and the accuracy of the numerical solution.

To minimize geometry discretization errors, triangular elements are used for modeling arbitrary package or board structures. Once an initial triangular mesh is generated with SIwave-DC, it is used as the input for the finite element solver to compute voltage distribution across the PDN for a given set of external sources and sinks. The accuracy of the numerical solution depends on the density and distribution of mesh elements as well as on the order of basis functions used within each mesh element. To control numerical solution accuracy in SIwave-DC, an h-type adaptive mesh refinement algorithm is used, similar to those employed in Ansys HFSS and Ansys Q3D Extractor. For a given mesh and given numerical solution for the mesh, the numerical error is computed within each mesh element, and the elements with the highest errors are selected for refinement. Mesh refinement splits these elements into smaller pieces. Once a new mesh is generated, the problem is solved again and the process repeats until the total numerical error is below the tolerance set by the user. This completely automated procedure, called automatic adaptive meshing, guarantees an optimal mesh (size and density distribution) and ensures an accurate solution with the fastest speed and lowest RAM utilization.

  • Analysis
    • DC voltage drop for all nets, including traces, ground and power
    • DC current hot-spot detection
    • Electromigration and warranty analysis
    • DC Power loss with thermal coupling to Ansys Icepack
  • Automatic adaptive mesh refinement ensures highly accurate, predictive analyses for chip, packages, and printed circuit boards that include ECAD primitives, such as planes, traces, vias, bondwires, solderballs and solderbumps
  • Path resistance from power sources to chips
  • Enhanced accuracy due to chip-level modeling for static DC losses
  • Bidirectional coupling to Ansys Icepak to calculate thermal losses
    • Automated reports for user-defined pass/fail criteria


Current and voltage distribution plots on VCC plane


Path resistance from VRM to different CPUs within PCB shown above: time and RAM required for automatically adaptive converged solution