ANSYS Chip-Package-System (CPS) design flow uses advanced modeling and proven simulator technologies to replace outdated compartmentalized design methodologies. CPS is an intelligent, integrated, chip-aware system design tool that can solve power integrity, signal integrity, EMI/EMC, ESD and thermal stress challenges.
Automated 3-D and layout assembly modeling for pre-layout and Chip-Package-System extraction combine with circuit simulation for full system verification.
ANSYS 17.0 introduces a unique layout assembly capability that integrates IC package layout, interposers, connectors, ribbon cables, flex cables and printed circuit board layout within a single assembly. This enables the Chip-Package-System design process to support new and existing mobile electronic devices. The streamlined CPS flow benefits from a new automated thermal analysis in which streamlined design flows analyze stresses, deformation and fatigue failures caused by high power densities.
Further solidifying the ANSYS advantage in CPS design is the new ultra-fast Chip Package Analysis (CPA) solver available within ANSYS SIwave. The SIwave-CPA solver quickly and accurately extracts power and signal nets on electronic packages. It can generate per-bump resolution SPICE models (thousands of bumps) along with user-defined pin grouped models that include ground bounce behavior. Additional advancements include crosstalk scanning and automated fault detection within signal integrity analyses, and 10x speed increase for package and board simulations using HPC technology. ANSYS integrated circuit tools provide key capabilities for power-thermal, power-performance, and reliability analysis. With ANSYS Redhawk, ANSYS Power Artist, and ANSYS Totem, you can optimize dynamic power performance and produce system models to be used in the full CPS flow process.
Request a Demo to see R17 in Action: