10x Total Gain in Productivity of Chip Power Integrity Analysis
The expanded implementation of DMP (distributed machine processing) to accelerate extraction and analysis offers close to 10x productivity improvement in both turnaround time and memory usage reduction. This 10x enhancement is valuable for advanced FinFET technologies, where sub-700 mV sign-off accuracy, full-chip plus package capacity, turnaround time and coverage are important requirements. Besides DMP, ANSYS’ capabilities include unique vectorless, chip-package co-analysis and optimization, along with thermal and ESD analyses. These features enable you to design SoCs with better power integrity and reliability for mobile, high-performance computing, communication and IoT applications.